The present invention generally relates to integrated circuits, and, more particularly, to a memory controller.
Integrated circuits (ICs) often include multiple cores for processing data packets and a shared memory for storing the data packets. ICs also include a memory controller that manages communication between the cores and the shared memory. To access the data packets stored in the memory, a core issues an access request that includes a memory address. The memory controller grants access to the core only after an on-going transaction of a former core with the memory is completed. Thus, due to contention, the core must wait before it can access the memory. This waiting period is referred to as the dynamic latency of the core.
A known technique to reduce dynamic latency involves interleaving of memory addresses, which requires the shared memory to be divided into multiple memory banks. Each memory bank is accessible, independent of other memory banks. Interleaving of addresses involves mapping contiguous addresses to memory locations in separate memory banks. The interleaving scheme may depend on the size of a contiguous address block mapped to each memory bank, for instance, interleaving based on a page size, a cache-line, and an address boundary. The cores generate access requests that include addresses mapped to memory locations present in separate memory banks due to interleaving of the addresses. Thus, address interleaving permits a core to sequentially access separate memory banks. Address interleaving also permits different cores to simultaneously access separate memory banks, leading to a reduction in dynamic latency. However, as only one core can access a memory bank in one access cycle, a memory access conflict arises when multiple cores try to simultaneously access the same memory bank.
A known technique to resolve memory access conflicts involves including an arbiter in the memory controller. The memory controller assigns a priority level to each core based on factors such as the core type and the access request type, and then provides the cores access to the memory based priority levels (i.e., the sequence of access for the cores).
To ensure fair access to the cores (i.e., to prevent starvation of low priority access requests), the arbiter can modify the access sequence using arbitration techniques such as rotating priority, round robin, and least recently accessed core. However, these arbitration techniques do not allow a user to dynamically determine the access sequence, and hence, a select logic circuit is included in the arbiter to allow a user to configure the access sequence. However, including such select logic requires redesigning the existing arbiter, which increases the complexity of the circuit and the circuit area.
It would be advantageous to have a memory controller that provides multiple cores access to the memory with reduced dynamic latency and contention and dynamically determines the access sequence without significantly increasing the complexity of the memory controller and the circuit area.